HD64F2357F20V Datasheet, PDF (289/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

8.3.8 Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single
transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
Figure 8-9 shows the memory map for chain transfer.
Source
DTC vector
address
Register information
start address
Register information
CHNE = 1
Register information
CHNE = 0
Destination
Source
Destination
Figure 8-9 Chain Transfer Memory Map
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified
number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not
affected.
Rev.6.00 Oct.28.2004 page 259 of 1016
REJ09B0138-0600H