HD64F2357F20V Datasheet, PDF (288/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

8.3.7 Block Transfer Mode
In block transfer mode, one operation transfers one block of data.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address
register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is
requested.
Table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory mapping in block transfer
mode.
Table 8-7 Register Information in Block Transfer Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Function
Designates transfer source address
Designates destination address
Holds block size
Designates block size count
Transfer count
SAR or
DAR
First block
·
·
Block area
·
Transfer
Nth block
DAR or
SAR
Figure 8-8 Memory Mapping in Block Transfer Mode
Rev.6.00 Oct.28.2004 page 258 of 1016
REJ09B0138-0600H