HD64F2357F20V Datasheet, PDF (539/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

• Serial data reception (clocked synchronous mode)
Figure 14-18 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER,
and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be
possible.
Initialization
Start reception
[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
Read ORER flag in SSR
[2] [3] Receive error processing:
[2]
If a receive error occurs, read the
ORER flag in SSR, and after
ORER= 1
Yes
[3]
performing the appropriate error
processing, clear the ORER flag
to 0. Transfer cannot be resumed
No
Error processing
if the ORER flag is set to 1.
[4] SCI status check and receive
(Continued below)
data read:
Read RDRF flag in SSR
[4]
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
No
RDRF= 1
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
Yes
an RXI interrupt.
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
<End>
[5] Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
[5]
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DMAC or
DTC is activated by a receive
data full interrupt (RXI) request
and the RDR value is read.
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
<End>
Figure 14-18 Sample Serial Reception Flowchart
Rev.6.00 Oct.28.2004 page 509 of 1016
REJ09B0138-0600H