HD64F2357F20V Datasheet, PDF (359/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Port F Data Register (PFDR)
Bit
:
Initial value :
R/W
:
7
PF7DR
0
R/W
6
PF6DR
0
R/W
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
0
PF0DR
0
R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF₇ to PF₀).
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port F Register (PORTF)
Bit
:
7
6
5
4
3
2
1
0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
Initial value : —*
—*
—*
—*
—*
—*
—*
—*
R/W
:
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PF₇ to PF₀.
PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port F pins (PF₇ to PF₀) must
always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while
PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and
PFDR are initialized. PORTF retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 329 of 1016
REJ09B0138-0600H