HD64F2357F20V Datasheet, PDF (114/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes
for the interrupt controller.
Bit 5
INTM1
0
1
Bit 4
INTM0
0
1
0
1
Interrupt
Control Mode
0
—
2
—
Description
Interrupts are controlled by I bit
(Initial value)
Setting prohibited
Interrupts are controlled by bits I2 to I0, and IPR
Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
0
1
Description
Interrupt request generated at falling edge of NMI input
Interrupt request generated at rising edge of NMI input
(Initial value)
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK)
Bit
:
7
—
Initial value :
0
R/W
:—
6
5
4
3
IPR6 IPR5 IPR4
—
1
1
1
0
R/W
R/W
R/W
—
2
IPR2
1
R/W
1
IPR1
1
R/W
0
IPR0
1
R/W
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than
NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5-3.
The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits cannot be modified and are always read as 0.
Rev.6.00 Oct.28.2004 page 84 of 1016
REJ09B0138-0600H