HD64F2357F20V Datasheet, PDF (875/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Address Register
(low) Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H’FFD0 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Module Name
TPU0
Data Bus
Width
16 bits
H’FFD1 TMDR0 —
—
BFB BFA MD3 MD2 MD1 MD0
H’FFD2 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H’FFD3 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
H’FFD4 TIER0 TTGE —
—
TCIEV TGIED TGIEC TGIEB TGIEA
H’FFD5 TSR0 —
—
—
TCFV TGFD TGFC TGFB TGFA
H’FFD6 TCNT0
H’FFD7
H’FFD8 TGR0A
H’FFD9
H’FFDA TGR0B
H’FFDB
H’FFDC TGR0C
H’FFDD
H’FFDE TGR0D
H’FFDF
H’FFE0 TCR1 —
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU1
16 bits
H’FFE1 TMDR1 —
—
—
—
MD3 MD2 MD1 MD0
H’FFE2 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H’FFE4 TIER1 TTGE —
TCIEU TCIEV —
—
TGIEB TGIEA
H’FFE5 TSR1 TCFD —
TCFU TCFV —
—
TGFB TGFA
H’FFE6 TCNT1
H’FFE7
H’FFE8 TGR1A
H’FFE9
H’FFEA TGR1B
H’FFEB
H’FFF0 TCR2 —
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2
16 bits
H’FFF1 TMDR2 —
—
—
—
MD3 MD2 MD1 MD0
H’FFF2 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H’FFF4 TIER2 TTGE —
TCIEU TCIEV —
—
TGIEB TGIEA
H’FFF5 TSR2 TCFD —
TCFU TCFV —
—
TGFB TGFA
H’FFF6 TCNT2
H’FFF7
H’FFF8 TGR2A
H’FFF9
H’FFFA TGR2B
H’FFFB
Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and
16 bits otherwise.
2. Applies to the H8S/2357 and H8S/2398.
3. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting,
the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for
group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for
group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
4. Functions as C/A for SCI use, and as GM for Smart Card interface use.
5. Functions as FER for SCI use, and as ERS for Smart Card interface use.
Rev.6.00 Oct.28.2004 page 845 of 1016
REJ09B0138-0600H