HD64F2357F20V Datasheet, PDF (320/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

P3DDR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after
a manual reset*, and in software standby mode. As the SCI is initialized, the pin states are determined by the P3DDR and
P3DR specifications.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 3 Data Register (P3DR)
Bit
:
7
6
5
—
— P35DR
Initial value : Undefined Undefined 0
R/W
:—
—
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
0
P30DR
0
R/W
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P3₅ to P3₀).
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
P3DR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a
manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 3 Register (PORT3)
Bit
:
7
6
5
4
3
2
1
0
—
—
P35
P34
P33
P32
P31
P30
Initial value : Undefined Undefined —*
—*
—*
—*
—*
—*
R/W
:—
—
R
R
R
R
R
R
Note: * Determined by state of pins P3₅ to P3₀.
PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3 pins (P3₅ to P3₀) must
always be performed on P3DR.
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while
P3DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin states, as P3DDR and
P3DR are initialized. PORT3 retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 3 Open Drain Control Register (P3ODR)
Bit
:
7
6
5
4
3
2
1
0
—
— P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Initial value : Undefined Undefined 0
0
0
0
0
0
R/W
:—
—
R/W
R/W
R/W
R/W
R/W
R/W
P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P3₅ to P3₀).
Rev.6.00 Oct.28.2004 page 290 of 1016
REJ09B0138-0600H