HD64F2357F20V Datasheet, PDF (840/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

A.4 Number of States Required for Instruction Execution
The tables in this section can be used to calculate the number of states required for instruction execution by the CPU.
Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table
A-4 indicates the number of states required for each cycle. The number of states required for execution of an instruction
can be calculated from these two tables as follows:
Execution states = I × S_I + J × S_J + K × S_K + L ×S_L + M × S_M + N × S_N
Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in
two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFC7:8
From table A-5:
I = L = 2, J = K = M = N = 0
From table A-4:
S_I = 4, S_L = 2
Number of states required for execution = 2 × 4 + 2 × 2 = 12
2. JSR @@30
From table A-5:
I = J = K = 2, L = M = N = 0
From table A-4:
S_I = S_J = S_K = 4
Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24
Table A-4 Number of States per Cycle
Access Conditions
On-Chip Supporting
Module
External Device
8-Bit Bus
16-Bit Bus
Cycle
On-Chip 8-Bit
Memory Bus
16-Bit
Bus
2-State 3-State 2-State 3-State
Access Access Access Access
Instruction fetch
S_I 1
4
2
Branch address read S_J
Stack operation
S_K
Byte data access S_L
2
Word data access S_M
4
Internal operation S_N 1
1
1
Legend:
m: Number of wait states inserted into external device access
4
6 + 2m 2
3+m
2
3+m
4
6 + 2m
1
1
1
1
Rev.6.00 Oct.28.2004 page 810 of 1016
REJ09B0138-0600H