HD64F2357F20V Datasheet, PDF (567/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received.
[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
[9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to
have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt
request is generated.
If data transfer by the DMAC or DTC by means of the TXI source is enabled, the next data can be written to TDR
automatically. When data is written to TDR by the DMAC or DTC, the TDRE bit is automatically cleared to 0.
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransferred frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer
frame n+1
Ds D0 D1 D2 D3 D4
TDRE
Transfer to TSR from TDR
TEND
FER/ERS
Transfer to TSR from TDR
[7]
[9]
[6]
[8]
Transfer to TSR
from TDR
Figure 15-12 Retransfer Operation in SCI Transmit Mode
Rev.6.00 Oct.28.2004 page 537 of 1016
REJ09B0138-0600H