HD64F2357F20V Datasheet, PDF (292/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

The number of execution states is calculated from the formula below. Note that Σ means the sum of all transfers activated
by one activation event (the number in which the CHNE bit is set to 1, plus 1).
Number of execution states = I · S_I + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred
from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from
activation to the end of the data write is 10 states.
8.3.11 Procedures for Using DTC
Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an
interrupt used as an activation source is generated.
[5] After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared
to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1.
Activation by Software: The procedure for using the DTC with software activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Check that the SWDTE bit is 0.
[4] Write 1 to SWDTE bit and the vector number to DTVECR.
[5] Check the vector number written to DTVECR.
[6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is
cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the
specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested.
8.3.12 Examples of Use of the D7TC
(1) Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
[1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal
mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by
one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the
data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
[2] Set the start address of the register information at the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
Rev.6.00 Oct.28.2004 page 262 of 1016
REJ09B0138-0600H