HD64F2357F20V Datasheet, PDF (572/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

16.2 Register Descriptions
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — —
Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
:R R R R R R R R R R R R R R R R
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored
there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits
are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in table 16-3.
ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is
performed via a temporary register (TEMP). For details, see section 16.3, Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode.
Table 16-3 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0
Group 1
AN0
AN4
AN1
AN5
AN2
AN6
AN3
AN7
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
16.2.2 A/D Control/Status Register (ADCSR)
Bit
:
Initial value :
R/W
:
7
ADF
0
R/(W)*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
Note: * Only 0 can be written to bit 7, to clear this flag.
3
CKS
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the
operation.
ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode.
Rev.6.00 Oct.28.2004 page 542 of 1016
REJ09B0138-0600H