HD64F2357F20V Datasheet, PDF (253/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Figure 7-24 shows an example of DREQ pin falling edge activated block transfer mode transfer.
Bus release
ø
DREQ
1 block transfer
DMA
read
DMA
write
DMA Bus
dead release
1 block transfer
DMA
read
DMA DMA Bus
write dead release
Address bus
Transfer
source
Transfer
destination
Transfer
source
Transfer
destination
DMA control
Channel
Idle
Read Write
Dead Idle Read Write
Dead
Request ^{Request clear period}
Minimun of 2 cycles
[1] [2] [3]
Request
Request clear period
Minimun of 2 cycles
[4] [5] [6]
Idle
[7]
Acceptance resumes
Acceptance resumes
[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ø,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of ø starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7-24 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling
for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends,
acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is
repeated until the transfer ends.
Rev.6.00 Oct.28.2004 page 223 of 1016
REJ09B0138-0600H