HD64F2357F20V Datasheet, PDF (458/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output):
Figure 11-7 shows an example in which pulse output is used for four-phase complementary non-overlapping pulse output.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
95
65
59
56
95
65
PODRH
PO15
00
95 05 65 41 59 50 56 14 95 05 65
Non-overlap margin
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Time
Figure 11-7 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
[1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers.
Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare
match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt.
[2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select
compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV
bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH.
[3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0.
When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value
set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH.
[4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95...
at successive TGIA interrupts. If the DTC or DMAC is set for activation by this interrupt, pulse output can be
obtained without imposing a load on the CPU.
Rev.6.00 Oct.28.2004 page 428 of 1016
REJ09B0138-0600H