HD64F2357F20V Datasheet, PDF (78/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

End of bus request
Bus request
End of bus
request
Bus-released state
End of
exception
handling
Program execution
state
Bus
request
SLEEP
instruction
with
SLEEP _{SSBY = 0}
instruction
with
SSBY = 1
Request for
exception
handling
Sleep mode
Exception-handling state
Interrupt
request
External interrupt
Software standby mode
RES = high
Reset state^*1
STBY = high, RES = low
Hardware standby mode^*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2-12 State Transitions
2.8.2 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The CPU enters the power-
on reset state when the NMI pin is high, or the manual reset* state when the NMI pin is low. All interrupts are masked in
the reset state. Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 13, Watchdog Timer.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset,
interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that
address.
(1) Types of Exception Handling and Their Priority
Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7 indicates the types of
exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution
state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Rev.6.00 Oct.28.2004 page 48 of 1016
REJ09B0138-0600H