HD64F2357F20V Datasheet, PDF (487/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as
an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a
watchdog timer, the WDT generates the WDTOVF signal*¹ when TCNT overflows.
Bit 6
WT/IT
Description
0
Interval timer: Sends the CPU an interval timer interrupt request (WOVI)
when TCNT overflows
(Initial value)
1
Watchdog timer: Generates the WDTOVF signal*¹ when TCNT overflows*²
Notes: 1. The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or
H8S/2390.
2. For details of the case where TCNT overflows in watchdog timer mode, see section 13.2.3, Reset
Control/Status Register (RSTCSR).
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME
0
1
Description
TCNT is initialized to H'00 and halted
TCNT counts
(Initial value)
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by
dividing the system clock (ø), for input to TCNT.
Description
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Clock
Overflow Period (when ø = 20 MHz)*
0
0
0
ø/2 (Initial value) 25.6 µs
1
ø/64
819.2 µs
1
0
ø/128
1.6 ms
1
ø/512
6.6 ms
1
0
0
ø/2048
26.2 ms
1
ø/8192
104.9 ms
1
0
ø/32768
419.4 ms
1
ø/131072
1.68 s
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs.
13.2.3 Reset Control/Status Register (RSTCSR)
Bit
:
7
6
5
4
3
2
1
0
WOVF RSTE RSTS
—
—
—
—
—
Initial value :
0
0
0
1
1
1
1
1
R/W
: R/(W)* R/W
R/W
—
—
—
—
—
Note: * Can only be written with 0 for flag clearing.
Rev.6.00 Oct.28.2004 page 457 of 1016
REJ09B0138-0600H