HD64F2357F20V Datasheet, PDF (695/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Table 20-4 and figure 20-6 show the input conditions for the external clock.
Table 20-4 External Clock Input Conditions
V_CC = 2.7 V V_CC = 5.0 V ±
to 5.5 V
10%
Item
Test
Symbol Min Max Min Max Unit Conditions
External clock input
t _EXL
low pulse width
40 — 20 — ns Figure 20-6
External clock input
t _EXH
high pulse width
40 — 20 — ns
External clock rise time t_EXr
External clock fall time t_EXf
Clock low pulse width t_CL
level
— 10 — 5 ns
— 10 — 5 ns
0.4 0.6 0.4 0.6 t_cyc
80 — 80 — ns
ø ≥ 5 MHz Figure 22-4
ø < 5 MHz
Clock high pulse width t_CH
level
0.4 0.6 0.4 0.6 t_cyc
80 — 80 — ns
ø ≥ 5 MHz
ø < 5 MHz
EXTAL
t_EXH
t_EXL
V_CC × 0.5
t_EXr
t_EXf
Figure 20-6 External Clock Input Timing
20.4 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal
from the oscillator to generate the system clock (ø).
20.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.
20.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed clocks (ø/2, ø/4, or ø/8,
ø/16, and ø/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR.
Rev.6.00 Oct.28.2004 page 665 of 1016
REJ09B0138-0600H