HD64F2357F20V Datasheet, PDF (593/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Section 19 ROM
19.1 Overview
This series has 256, or 128 kbytes of flash memory, 256 or 128 kbytes of masked ROM, or 128 kbytes of PROM. The
ROM is connected to the H8S/2000 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one
state, making possible rapid instruction fetches and high-speed processing.
The on-chip ROM is enabled or disabled by setting the mode pins (MD₂, MD₁, and MD₀) and bit EAE in BCRL.
The flash memory versions of the H8S/2357 Group can be erased and programmed on-board as well as with a PROM
programmer.
The PROM version of the H8S/2357 Group can be programmed with a PROM programmer, by setting PROM mode.
19.1.1 Block Diagram
Figure 19-1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'000001
H'000003
H'01FFFE
H'01FFFF
Figure 19-1 Block Diagram of ROM (128 kbytes)
19.1.2 Register Configuration
The H8S/2357’s on-chip ROM is controlled by the mode pins and register BCRL. The register configuration is shown in
table 19-1.
Table 19-1 ROM Register
Name
Mode control register
Bus control register L
Note: * Lower 16 bits of the address.
Abbreviation
R/W
MDCR
R/W
BCRL
R/W
Initial Value
Undefined
Undefined
Address*
H'FF3B
H'FED5
Rev.6.00 Oct.28.2004 page 563 of 1016
REJ09B0138-0600H