HD64F2357F20V Datasheet, PDF (536/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Data Transfer Operations:
• SCI initialization (clocked synchronous mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as
described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized.
Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the
contents of RDR.
Figure 14-15 shows a sample SCI initialization flowchart.
Start initialization
Clear TE and RE bits in SCR to 0
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
[2] Set the data transfer format in SMR
and SCMR.
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
Set data transfer format in
SMR and SCMR
Set value in BRR
Wait
1-bit interval elapsed?
[1] _{[3] Write a value corresponding to the bit}
rate to BRR. Not necessary if an
external clock is used.
[2] _{[4] Wait at least one bit interval, then set}
the TE bit or RE bit in SCR to 1.
[3]
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
No
Yes
Set TE and RE bits in SCR to 1, and _[4]
set RIE, TIE, TEIE, and MPIE bits
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should
both be cleared to 0 or set to 1 simultaneously.
Figure 14-15 Sample SCI Initialization Flowchart
Rev.6.00 Oct.28.2004 page 506 of 1016
REJ09B0138-0600H