HD64F2357F20V Datasheet, PDF (755/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Item
Symbol Min Typ Max Unit
Test
Condition
Programming Wait time after SWE bit clear*¹ θ
100 — —
µs
Maximum programming
count*¹*⁴
N
— — 1000*⁵ Times
Erase
Wait time after SWE bit
setting*¹
x
1 ——
µs
Wait time after ESU bit
setting*¹
y
100 — —
µs
Wait time after E bit setting*¹*⁶ z
— — 10
ms
Erase time
wait
Wait time after E bit clear*¹
α
10 — —
µs
Wait time after ESU bit clear*¹ β
10 — —
µs
Wait time after EV bit setting*¹ γ
20 — —
µs
Wait time after H’FF dummy ε
write*¹
2 ——
µs
Wait time after EV bit clear*¹ η
4 ——
µs
Wait time after SWE bit clear*¹ θ
100 — —
µs
Maximum erase count*¹*⁶
N
— — 100 Times
Notes: 1. Settings of each time must comply with algorithm of writing/erasing.
2. Writing time for 128 bytes: indicates the total period in which bit P of flash memory control register 1 (FLMCR1)
is set. Writing verification time is not included.
3. Erasing time for one block: indicates the period in which bit E of FLMCR1 is set. Erasing verification time is not
included.
4. Maximum writing time: t_P(max) = Σ wait time (z) after setting of bit P
5. The maximum writing count (N) must be set to the maximum writing time (t_P(max)) or less according the actual
set value (z). Wait time (z) must be switched after setting of bit P according to writing count (n).
Writing count n
1≤n≤6
z = 30 µs
7 ≤ n ≤ 1000 z = 200 µs
[In additional writing]
Writing count n
1≤n≤6
z = 10 µs
6. Wait time (z) after setting of bit E and the maximum erasing count (N) have the following relationship to the
maximum erasing time (t_E(max)).
t_E(max) = wait time (z) after setting of bit E × maximum erasing count (N)
Rev.6.00 Oct.28.2004 page 725 of 1016
REJ09B0138-0600H