HD64F2357F20V Datasheet, PDF (82/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Bus cycle
T1
ø
Address bus
Unchanged
AS
High
RD
High
HWR, LWR
High
Data bus
High-impedance state
Figure 2-15 Pin States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the
particular internal I/O register being accessed. Figure 2-16 shows the access timing for the on-chip supporting modules.
Figure 2-17 shows the pin states.
Bus cycle
T1
T2
ø
Internal address bus
Address
Read
access
Internal read signal
Internal data bus
Write
access
Internal write signal
Internal data bus
Read data
Write data
Figure 2-16 On-Chip Supporting Module Access Cycle
Rev.6.00 Oct.28.2004 page 52 of 1016
REJ09B0138-0600H