HD64F2357F20V Datasheet, PDF (376/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Bits 7 to 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing
source.
Channel
0, 3
Bit 7
CCLR2
0
1
Bit 6
CCLR1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Description
TCNT clearing disabled
(Initial value)
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *¹
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture *²
TCNT cleared by TGRD compare match/input
capture *²
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *¹
Bit 7
Bit 6
Channel Reserved*³ CCLR1
Bit 5
CCLR0
Description
1, 2, 4, 5 0
0
0
TCNT clearing disabled
(Initial value)
1
TCNT cleared by TGRA compare match/input
capture
1
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *¹
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has
priority, and compare match/input capture does not occur.
3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified.
Rev.6.00 Oct.28.2004 page 346 of 1016
REJ09B0138-0600H