HD64F2357F20V Datasheet, PDF (242/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Figure 7-14 illustrates operation in block transfer mode when MARA is designated as a block area.
Address TA
Address BA
Block area
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
1st block
2nd block
Address T_B
Legend:
Address TA = LA
Address TB = LB
Address BA = LA + SAIDE · (–1)^SAID · (2^DTSZ · (N–1))
Address BB = LB + DAIDE · (–1)^DAID · (2^DTSZ · (M·N–1))
Where : LA = Value set in MARA
LB = Value set in MARB
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
Nth block
Address B_B
Figure 7-14 Operation in Block Transfer Mode (BLKDIR = 1)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request,
burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH.
At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA
is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer
ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC.
Figure 7-15 shows the operation flow in block transfer mode.
Rev.6.00 Oct.28.2004 page 212 of 1016
REJ09B0138-0600H