HD64F2357F20V Datasheet, PDF (19/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

7.3.1 Memory Address Register (MAR) ..............................................................................................................181
7.3.2 I/O Address Register (IOAR)......................................................................................................................181
7.3.3 Execute Transfer Count Register (ETCR)................................................................................................... 181
7.3.4 DMA Control Register (DMACR)..............................................................................................................183
7.3.5 DMA Band Control Register (DMABCR)..................................................................................................186
7.4 Register Descriptions (3) ..........................................................................................................................................190
7.4.1 DMA Write Enable Register (DMAWER) ................................................................................................. 190
7.4.2 DMA Terminal Control Register (DMATCR)............................................................................................192
7.4.3 Module Stop Control Register (MSTPCR) ................................................................................................. 193
7.5 Operation ..................................................................................................................................................................194
7.5.1 Transfer Modes ........................................................................................................................................... 194
7.5.2 Sequential Mode..........................................................................................................................................196
7.5.3 Idle Mode..................................................................................................................................................... 199
7.5.4 Repeat Mode ............................................................................................................................................... 201
7.5.5 Single Address Mode ..................................................................................................................................204
7.5.6 Normal Mode............................................................................................................................................... 207
7.5.7 Block Transfer Mode................................................................................................................................... 210
7.5.8 DMAC Activation Sources ......................................................................................................................... 215
7.5.9 Basic DMAC Bus Cycles ............................................................................................................................217
7.5.10 DMAC Bus Cycles (Dual Address Mode) ..................................................................................................218
7.5.11 DMAC Bus Cycles (Single Address Mode) ............................................................................................... 226
7.5.12 Write Data Buffer Function......................................................................................................................... 230
7.5.13 DMAC Multi-Channel Operation ............................................................................................................... 231
7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC ............................... 232
7.5.15 NMI Interrupts and DMAC......................................................................................................................... 233
7.5.16 Forced Termination of DMAC Operation................................................................................................... 234
7.5.17 Clearing Full Address Mode ....................................................................................................................... 235
7.6 Interrupts................................................................................................................................................................... 236
7.7 Usage Notes ..............................................................................................................................................................237
Section 8 Data Transfer Controller ...................................................................................................241
8.1 Overview................................................................................................................................................................... 241
8.1.1 Features ....................................................................................................................................................... 241
8.1.2 Block Diagram............................................................................................................................................. 242
8.1.3 Register Configuration ................................................................................................................................243
8.2 Register Descriptions................................................................................................................................................244
8.2.1 DTC Mode Register A (MRA)....................................................................................................................244
8.2.2 DTC Mode Register B (MRB) ....................................................................................................................245
8.2.3 DTC Source Address Register (SAR)......................................................................................................... 246
8.2.4 DTC Destination Address Register (DAR) ................................................................................................. 246
8.2.5 DTC Transfer Count Register A (CRA) ..................................................................................................... 246
8.2.6 DTC Transfer Count Register B (CRB) ......................................................................................................246
8.2.7 DTC Enable Registers (DTCER) ................................................................................................................247
8.2.8 DTC Vector Register (DTVECR) ............................................................................................................... 247
8.2.9 Module Stop Control Register (MSTPCR) ................................................................................................. 248
8.3 Operation ..................................................................................................................................................................249
8.3.1 Overview ..................................................................................................................................................... 249
8.3.2 Activation Sources....................................................................................................................................... 251
8.3.3 DTC Vector Table ....................................................................................................................................... 252
8.3.4 Location of Register Information in Address Space ................................................................................... 255
8.3.5 Normal Mode............................................................................................................................................... 256
8.3.6 Repeat Mode ............................................................................................................................................... 257
Rev.6.00 Oct.28.2004 page xiii of xxiv
REJ09B0138-0600H