HD64F2357F20V Datasheet, PDF (225/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Operation in each mode is summarized below.
(1) Sequential mode
In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a
time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been
completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable.
(2) Idle mode
In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a
time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been
completed. One address is specified as 24 bits, and the other as 16 bits. The transfer source address and transfer
destination address are fixed. The transfer direction is programmable.
(3) Repeat mode
In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a
time. When the specified number of transfers have been completed, the addresses and transfer counter are restored to
their original settings, and operation is continued. No interrupt request is sent to the CPU or DTC. One address is
specified as 24 bits, and the other as 16 bits. The transfer direction is programmable.
(4) Single address mode
In response to a single transfer request, the specified number of transfers are carried out between external memory and
an external device, one byte or one word at a time. Unlike dual address mode, source and destination accesses are
performed in parallel. Therefore, either the source or the destination is an external device which can be accessed with a
strobe alone, using the DACK pin. One address is specified as 24 bits, and for the other, the pin is set automatically.
The transfer direction is programmable.
Modes (1), (2) and (3) can also be specified for single address mode.
(5) Normal mode
• Auto-request
By means of register settings only, the DMAC is activated, and transfer continues until the specified number of
transfers have been completed. An interrupt request can be sent to the CPU or DTC when transfer is completed. Both
addresses are specified as 24 bits.
 Cycle steal mode: The bus is released to another bus master every byte or word transfer.
 Burst mode: The bus is held and transfer continued until the specified number of transfers have been completed.
• External request
In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a
time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been
completed. Both addresses are specified as 24 bits.
(6) Block transfer mode
In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the
specified number of times, once each time there is a transfer request. At the end of each single block transfer, one
address is restored to its original setting. An interrupt request can be sent to the CPU or DTC when the specified
number of block transfers have been completed. Both addresses are specified as 24 bits.
Rev.6.00 Oct.28.2004 page 195 of 1016
REJ09B0138-0600H