HD64F2357F20V Datasheet, PDF (148/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

6.2.7 DRAM Control Register (DRAMCR)
Bit
:
Initial value :
R/W
:
7
RFSHE
0
R/W
6
RCW
0
R/W
5
RMODE
0
R/W
4
CMF
0
R/W
3
CMIE
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and
controls the refresh timer.
DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset*
or in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When refresh control is not
performed, the refresh timer can be used as an interval timer.
Bit 7
RFSHE
0
1
Description
Refresh control is not performed
Refresh control is performed
(Initial value)
Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before-RAS refreshing.
Bit 6
RCW
0
1
Description
Wait state insertion in CAS-before-RAS refreshing disabled
RAS falls in T_Rr cycle
One wait state inserted in CAS-before-RAS refreshing
RAS falls in T_Rc1 cycle
(Initial value)
Bit 5—Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), this bit selects whether normal
refreshing (CAS-before-RAS refreshing for the DRAM interface) or self-refreshing is performed.
Bit 5
RMODE
0
1
Description
DRAM interface
CAS-before-RAS refreshing used
Self-refreshing used
(Initial value)
Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR.
When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR.
Bit 4
CMF
0
1
Description
[Clearing condition]
Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag
(Initial value)
[Setting condition]
Set when RTCNT = RTCOR
Rev.6.00 Oct.28.2004 page 118 of 1016
REJ09B0138-0600H