HD64F2357F20V Datasheet, PDF (72/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Table 2-4 Addressing Modes
No.
Addressing Mode
1
Register direct
2
Register indirect
3
Register indirect with displacement
4
Register indirect with post-increment
Register indirect with pre-decrement
5
Absolute address
6
Immediate
7
Program-counter relative
8
Memory indirect
Symbol
Rn
@ERn
@(d:16,ERn)/@(d:32,ERn)
@ERn+
@–ERn
@aa:8/@aa:16/@aa:24/@aa:32
#xx:8/#xx:16/#xx:32
@(d:8,PC)/@(d:16,PC)
@@aa:8
(1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit
registers. ER0 to ER7 can be specified as 32-bit registers.
(2) Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn) which
contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid
and the upper 8 bits are all assumed to be 0 (H'00).
(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained
in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives
the address of a memory operand. A 16-bit displacement is sign-extended when added.
(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) which contains the address of a memory
operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For word or longword transfer instruction, the register value should be even.
• Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code,
and the result becomes the address of a memory operand. The result is also stored in the address register. The value
subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or
longword transfer instruction, the register value should be even.
(5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a
memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32
bits long (@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit
absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a
sign extension. A 32-bit absolute address can access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0
(H'00).
Table 2-5 indicates the accessible absolute address ranges.
Rev.6.00 Oct.28.2004 page 42 of 1016
REJ09B0138-0600H