HD64F2357F20V Datasheet, PDF (479/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

12.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write takes priority and the
counter is not incremented.
Figure 12-11 shows this operation.
TCNT write cycle by CPU
T₁
T₂
ø
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12-11 Contention between TCNT Write and Increment
Rev.6.00 Oct.28.2004 page 449 of 1016
REJ09B0138-0600H