HD64F2357F20V Datasheet, PDF (389/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Bit 3 Bit 2 Bit 1 Bit 0
Channel IOA3 IOA2 IOA1 IOA0 Description
3
0 0 0 0 TGR3A is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1 0 0 0 TGR3A is Capture input Input capture at rising edge
1
input
source is
capture TIOCA3 pin
1
×
register
Input capture at falling edge
Input capture at both edges
1
×
×
Capture input Input capture at TCNT4
source is channel count-up/count-down
4/count clock
×: Don’t care
Bit 3 Bit 2 Bit 1 Bit 0
Channel IOC3 IOC2 IOC1 IOC0 Description
3
0 0 0 0 TGR3C is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register*¹
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1 0 0 0 TGR3C is Capture input Input capture at rising edge
1
input
source is
capture TIOCC3 pin
1
×
register*
Input capture at falling edge
Input capture at both edges
1
×
×
Capture input Input capture at TCNT4
source is channel count-up/count-down
4/count clock
×: Don’t care
Note: * When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
Rev.6.00 Oct.28.2004 page 359 of 1016
REJ09B0138-0600H