HD64F2357F20V Datasheet, PDF (158/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

6.4.4 Basic Timing
8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access
space is accessed, the upper half (D₁₅ to D₈) of the data bus is used.
The LWR pin is fixed high. Wait states cannot be inserted.
Bus cycle
T₁
T₂
ø
Address bus
CSn
AS
RD
Read
D₁₅ to D₈
Valid
D₇ to D₀
Invalid
HWR
Write
LWR
D₁₅ to D₈
D₇ to D₀
Note: n = 0 to 7
High
Valid
High impedance
Figure 6-6 Bus Timing for 8-Bit 2-State Access Space
Rev.6.00 Oct.28.2004 page 128 of 1016
REJ09B0138-0600H