HD64F2357F20V Datasheet, PDF (468/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests (OVI) are enabled or
disabled when the OVF flag of TCSR is set to 1.
Bit 5
OVIE
0
1
Description
OVF interrupt requests (OVI) are disabled
OVF interrupt requests (OVI) are enabled
(Initial value)
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by which TCNT is cleared:
by compare match A or B, or by an external reset input.
Bit 4
CCLR1
0
1
Bit 3
CCLR0
0
1
0
1
Description
Clear is disabled
Clear by compare match A
Clear by compare match B
Clear by rising edge of external reset input
(Initial value)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or
external clock.
Three internal clocks can be selected, all divided from the system clock (ø): ø/8, ø/64, and ø/8192. The falling edge of the
selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and
both rising and falling edges.
Some functions differ between channel 0 and channel 1.
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Description
0
0
0
Clock input disabled
(Initial value)
1
Internal clock, counted at falling edge of ø/8
1
0
Internal clock, counted at falling edge of ø/64
1
Internal clock, counted at falling edge of ø/8192
1
0
0
For channel 0: count at TCNT1 overflow signal*
For channel 1: count at TCNT0 compare match A*
1
External clock, counted at rising edge
1
0
External clock, counted at falling edge
1
External clock, counted at both rising and falling edges
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match
signal, no incrementing clock is generated. Do not use this setting.
Rev.6.00 Oct.28.2004 page 438 of 1016
REJ09B0138-0600H