HD64F2357F20V Datasheet, PDF (506/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Note:
Bit 6
RDRF
Description
0
[Clearing conditions]
(Initial value)
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC or DTC is activated by an RXI interrupt and read data from RDR
1
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception
or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the
receive data will be lost.
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal
termination.
Bit 5
ORER
Description
0
[Clearing condition]
(Initial value)*¹
When 0 is written to ORER after reading ORER = 1
1
[Setting condition]
When the next serial reception is completed while RDRF = 1*²
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also,
subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued, either.
Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing
abnormal termination.
Bit 4
FER
Description
0
[Clearing condition]
(Initial value)*¹
When 0 is written to FER after reading FER = 1
1
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive data when
reception ends, and the stop bit is 0 *²
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a
framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
Rev.6.00 Oct.28.2004 page 476 of 1016
REJ09B0138-0600H