HD64F2357F20V Datasheet, PDF (921/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

ISR—IRQ Status Register
H'FF2F
Interrupt Controller
Bit
:
Initial value :
Read/Write :
7
IRQ7F
0
R/(W)*
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
Indicate the status of IRQ7 to IRQ0 interrupt requests
Note: * Can only be written with 0 for flag clearing.
DTCERA to DTCERF—DTC Enable Registers H'FF30 to H'FF35
DTC
Bit
:
Initial value :
Read/Write :
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
0
DTCE0
0
R/W
DTC Activation Enable
DTC activation by this interrupt is disabled
0 [Clearing conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
DTC activation by this interrupt is enabled
1 ^{[Holding condition]}
When the DISEL bit is 0 and the specified number of
transfers have not ended
Correspondence between Interrupt Sources and DTCER
Register
DTCERA
DTCERB
DTCERC
DTCERD
DTCERE
DTCERF
Bits
7
6
5
4
3
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
—
ADI
TGI0A
TGI0B
TGI0C
TGI2A
TGI2B
TGI3A
TGI3B
TGI3C
—
—
TGI5A
TGI5B
CMIA0
DMTEND0A DMTEND0B DMTEND1A DMTEND1B RXI0
RXI2
TXI2
—
—
—
2
IRQ5
TGI0D
TGI3D
CMIB0
TXI0
—
1
IRQ6
TGI1A
TGI4A
CMIA1
RXI1
—
0
IRQ7
TGI1B
TGI4B
CMIB1
TXI1
—
Rev.6.00 Oct.28.2004 page 891 of 1016
REJ09B0138-0600H