HD64F2357F20V Datasheet, PDF (169/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

6.5.5 Pins Used for DRAM Interface
Table 6-7 shows the pins used for DRAM interfacing and their functions.
Table 6-7 DRAM Interface Pins
Pin
HWR
LCAS
CS2
CS3
CS4
CS5
CAS
WAIT
A₁₂ to A₀
D₁₅ to D₀
With DRAM
Setting
WE
LCAS
RAS2
RAS3
RAS4
RAS5
UCAS
WAIT
A₁₂ to A₀
D₁₅ to D₀
Name
I/O
Function
Write enable
Output When 2-CAS system is set,
write enable for DRAM space
access.
Lower column address strobe Output Lower column address strobe
for 16-bit DRAM space access
Row address strobe 2
Output Row address strobe when
area 2 is designated as DRAM
space.
Row address strobe 3
Output Row address strobe when
area 3 is designated as DRAM
space.
Row address strobe 4
Output Row address strobe when
area 4 is designated as DRAM
space.
Row address strobe 5
Output Row address strobe when
area 5 is designated as DRAM
space.
Upper column address strobe Output Upper column address strobe
for DRAM space access
Wait
Input Wait request signal
Address pins
Output Row address/column address
multiplexed output
Data pins
I/O
Data input/output pins
Rev.6.00 Oct.28.2004 page 139 of 1016
REJ09B0138-0600H