HD64F2357F20V Datasheet, PDF (178/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

T_Rp
T_Rr
T_Rc1
T_Rc2
ø
CS, (RAS)
CAS, LCAS
Note: n = 2 to 5
Figure 6-25 CBR Refresh Timing
When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted
with bits RLW1 and RLW0. These bits are only enabled in refresh operations.
Figure 6-26 shows the timing when the RCW bit is set to 1.
T_Rp
T_Rr
T_Rc1
T_Rw
T_Rc2
ø
CSn, (RAS)
CAS, LCAS
Note: n = 2 to 5
Figure 6-26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1)
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this
mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a SLEEP instruction is
executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as
shown in figure 6-27.
When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is cleared.
When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is executed before self-
refresh mode is entered.
Rev.6.00 Oct.28.2004 page 148 of 1016
REJ09B0138-0600H