HD64F2357F20V Datasheet, PDF (125/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

5.4.3 Interrupt Control Mode 2
Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the
interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR.
Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the
interrupt controller.
[2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the
interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of
interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority
according to the priority system shown in table 5-4 is selected.
[3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt
request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with
a priority higher than the interrupt mask level is accepted.
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has
been completed.
[5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows
the address of the first instruction to be executed after returning from the interrupt handling routine.
[6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the
address indicated by the contents of that vector address.
Rev.6.00 Oct.28.2004 page 95 of 1016
REJ09B0138-0600H