HD64F2357F20V Datasheet, PDF (248/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

7.5.10 DMAC Bus Cycles (Dual Address Mode)
Short Address Mode: Figure 7-19 shows a transfer example in which TEND output is enabled and byte-size short
address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O
space.
ø
Address bus
RD
HWR
LWR
TEND
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA DMA
write dead
Bus release
Bus release
Bus release Last transfer cycle
Bus
release
Figure 7-19 Example of Short Address Mode Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the
bus is released one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after
the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in which the transfer counter
reaches 0.
Rev.6.00 Oct.28.2004 page 218 of 1016
REJ09B0138-0600H