HD64F2357F20V Datasheet, PDF (160/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit
access space is accessed, the upper half (D₁₅ to D₈) of the data bus is used for the even address, and the lower half (D₇ to
D₀) for the odd address.
Wait states cannot be inserted.
Bus cycle
T₁
T₂
ø
Address bus
CSn
AS
RD
Read
D₁₅ to D₈
Valid
D₇ to D₀
Invalid
HWR
Write
LWR
D₁₅ to D₈
D₇ to D₀
Note: n = 0 to 7
High
Valid
High impedance
Figure 6-8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
Rev.6.00 Oct.28.2004 page 130 of 1016
REJ09B0138-0600H