HD64F2357F20V Datasheet, PDF (291/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

ø
DTC activation
request
DTC
request
Address
Vector read
Data transfer
Read Write
Data transfer
Read Write
Transfer
information
read
Transfer Transfer
information information
write
read
Transfer
information
write
Figure 8-12 DTC Operation Timing (Example of Chain Transfer)
8.3.10 Number of DTC Execution States
Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for
each execution status.
Table 8-8 DTC Execution Statuses
Mode
Normal
Repeat
Block transfer
Vector Read
I
1
1
1
Register Information
Internal
Read/Write
Data Read Data Write Operations
J
K
L
M
6
1
1
3
6
1
1
3
6
N
N
3
N: Block size (initial setting of CRAH and CRAL)
Table 8-9 Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
Execution Vector read
S_I
status
Register
S_J
information
read/write
Byte data read S_K
Word data read S_K
Byte data write S_L
Word data write S_L
Internal operation S_M
On- On-
Chip Chip On-Chip I/O
RAM ROM Registers
32 16 8
16
1
1
2
2
—1
——
1
———
External Devices
8
16
2
3
2
4
6+2m 2
———
1
1
2
2
2
3+m 2
1
1
4
2
4
6+2m 2
1
1
2
2
2
3+m 2
1
1
4
2
4
6+2m 2
1
3
3+m
—
3+m
3+m
3+m
3+m
Rev.6.00 Oct.28.2004 page 261 of 1016
REJ09B0138-0600H