HD64F2357F20V Datasheet, PDF (505/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

For details of clock source selection, see table 14-9 in section 14.3, Operation.
Bit 1 Bit 0
CKE1 CKE0 Description
0
0
Asynchronous mode
Internal clock/SCK pin functions as I/O port*¹
Clocked synchronous
mode
Internal clock/SCK pin functions as serial clock
output
1
Asynchronous mode
Internal clock/SCK pin functions as clock output*²
Clocked synchronous
mode
Internal clock/SCK pin functions as serial clock
output
1
0
Asynchronous mode
External clock/SCK pin functions as clock input*³
Clocked synchronous
mode
External clock/SCK pin functions as serial clock
input
1
Asynchronous mode
External clock/SCK pin functions as clock input*³
Clocked synchronous
mode
External clock/SCK pin functions as serial clock
input
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
14.2.7 Serial Status Register (SSR)
Bit
:
Initial value :
R/W
:
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
Note: * Only 0 can be written, to clear the flag.
1
MPB
0
R
0
MPBT
0
R/W
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER,
and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are
read-only flags and cannot be modified.
SSR is initialized to H'84 by a reset, and by putting the device in standby mode or module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next
serial data can be written to TDR.
Bit 7
TDRE
0
1
Description
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
(Initial value)
• When data is transferred from TDR to TSR and data can be written to TDR
Rev.6.00 Oct.28.2004 page 475 of 1016
REJ09B0138-0600H