HD64F2357F20V Datasheet, PDF (885/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

TGR3A—Timer General Register 3A
TGR3B—Timer General Register 3B
TGR3C—Timer General Register 3C
TGR3D—Timer General Register 3D
H'FE88
H'FE8A
H'FE8C
H'FE8E
TPU3
TPU3
TPU3
TPU3
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCR4—Timer Control Register 4
H'FE90
TPU4
Bit
:
Initial value :
Read/Write :
7
6
5
4
3
2
1
0
— CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer Prescaler
0 0 0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKC pin input
1 0 Internal clock: counts on ø/1024
1 Counts on TCNT5 overflow/underflow
Clock Edge
Note: This setting is ignored when channel 4 is in phase
counting mode.
0 0 Count at rising edge
1 Count at falling edge
1 — Count at both edges
Counter Clear
Note: This setting is ignored when channel
4 is in phase counting mode.
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 _{TCNT cleared by counter clearing for another channel}
performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting
the SYNC bit TSYR to 1.
Rev.6.00 Oct.28.2004 page 855 of 1016
REJ09B0138-0600H