HD64F2357F20V Datasheet, PDF (1039/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

MCU
Port Name Operating
Pin Name Mode
PF₂/LCAS/
WAIT/
BREQO
4 to 6
7
PF₁/BACK 4 to 6
7
PF₀/BREQ 4 to 6
PG₄/CS0 4, 5
6
Power-
On
Manual
Reset Reset*²
Hardware Software
Standby Standby
Mode Mode
Bus
Release
State
Program
Execution
State
Sleep Mode
T
[BREQOE + T
WAITE +
LCASE = 0]
kept
[BREQOE = 1]
BREQO
[WAITE = 1]
T
[LCASE = 1]
H*¹
[BREQOE +
WAITE +
LCASE = 0]
kept
[BREQOE = 1]
kept
[WAITE = 1]
T
[LCASE = 1,
OPE = 0]
T
[LCASE = 1,
OPE = 1]
LCAS
[BREQOE + [BREQOE +
WAITE +
WAITE +
LCASE = 0] LCASE= 0]
kept
I/O port
[BREQOE = 1] [BREQOE = 1]
BREQO
BREQO
[WAITE = 1] [WAITE = 1]
T
WAIT
[LCASE = 1] [LCASE = 1]
T
LCAS
T
kept
T
kept
kept
I/O port
T
[BRLE = 0] T
kept
[BRLE = 1]
BACK
[BRLE = 0]
L
kept
[BRLE = 1]
H
[BRLE = 0]
I/O port
[BRLE = 1]
BACK
T
kept
T
kept
kept
I/O port
T
[BRLE = 0] T
kept
[BRLE = 1]
BREQ
[BRLE = 0]
T
kept
[BRLE = 1]
T
[BRLE = 0]
I/O port
[BRLE = 1]
BREQ
H
[DDR = 0] T
T
T
[DDR = 1]
H*¹
[DDR · OPE = 0] T
T
[DDR · OPE = 1]
H
[DDR = 0]
Input port
[DDR = 1]
CS0
7
T
kept
T
kept
kept
I/O port
PG₃/CS1
PG₂/CS2
PG₁/CS3
7
4 to 6
T
kept
T
T
[DDR = 0] T
T
[DDR = 1]
H*¹
kept
kept
[DDR · OPE = 0] T
T
[DDR · OPE = 1]
H
I/O port
[DDR = 0]
Input port
[DDR = 1]
CS1 to CS3
PG₀/CAS 7
T
kept
T
kept
kept
4 to 6
T
[DRAME = 0] T
kept
[DRAME = 1]
H*¹
[DRAME = 0] T
kept
[OPE = 0]
T
[DRAME ·
OPE= 1]
CAS
Legend:
H:
L:
T:
kept:
DDR:
OPE:
WAITE:
BRLE:
High level
Low level
High impedance
Input port becomes high-impedance, output port retains state
Data direction register
Output port enable
Wait input enable
Bus release enable
I/O port
[DRAME = 0]
Input port
[DRAME = 1]
CAS
Rev.6.00 Oct.28.2004 page 1009 of 1016
REJ09B0138-0600H