HD64F2357F20V Datasheet, PDF (204/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

7.2.4 DMA Control Register (DMACR)
Bit
:
DMACR :
Initial value :
R/W
:
7
DTSZ
0
R/W
6
DTID5
0
R/W
5
RPE
0
R/W
4
DTDIR
0
R/W
3
DTF3
0
R/W
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
DMACR is initialized to H'00 by a reset, and in hardware standby mode.
Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 7
DTSZ
0
1
Description
Byte-size transfer
Word-size transfer
(Initial value)
Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR every data transfer
in sequential mode or repeat mode.
In idle mode, MAR is neither incremented nor decremented.
Bit 6
DTID
0
1
Description
MAR is incremented after a data transfer
• When DTSZ = 0, MAR is incremented by 1 after a transfer
• When DTSZ = 1, MAR is incremented by 2 after a transfer
MAR is decremented after a data transfer
• When DTSZ = 0, MAR is decremented by 1 after a transfer
• When DTSZ = 1, MAR is decremented by 2 after a transfer
(Initial value)
Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle,
or repeat) in which transfer is to be performed.
Bit 5
RPE
0
1
DMABCR
DTIE
Description
0
Transfer in sequential mode (no transfer end interrupt)
1
Transfer in sequential mode (with transfer end interrupt)
0
Transfer in repeat mode (no transfer end interrupt)
1
Transfer in idle mode (with transfer end interrupt)
(Initial value)
For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode, section 7.5.3, Idle Mode,
and section 7.5.4, Repeat Mode.
Rev.6.00 Oct.28.2004 page 174 of 1016
REJ09B0138-0600H