HD64F2357F20V Datasheet, PDF (334/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Port A Open Drain Control Register (PAODR) (On-Chip ROM Version Only)
Bit
:
7
6
5
4
3
2
1
0
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA₇ to PA₀).
All bits are valid in mode 7.
Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0
makes the pin a CMOS output.
PAODR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
9.8.3 Pin Functions
Mode 7 (On-Chip ROM Version Only): In mode 7, port A pins function as I/O ports and interrupt input pins. Input or
output can be specified for each pin on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A
pin an output port, while clearing the bit to 0 makes the pin an input port.
Port A pin functions in mode 7 are shown in figure 9-8.
Port A
PA₇ (I/O)/IRQ7 (input)
PA₆ (I/O)/IRQ6 (input)
PA₅ (I/O)/IRQ5 (input)
PA₄ (I/O)/IRQ4 (input)
PA₃ (I/O)
PA₂ (I/O)
PA₁ (I/O)
PA₀ (I/O)
Figure 9-8 Port A Pin Functions (Mode 7)
Rev.6.00 Oct.28.2004 page 304 of 1016
REJ09B0138-0600H