HD64F2357F20V Datasheet, PDF (332/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

9.8.2 Register Configuration
Table 9-13 shows the port A register configuration.
Table 9-13 Port A Registers
Name
Abbreviation R/W Initial Value
Port A data direction register
PADDR
W
H'00
Port A data register
PADR
R/W H'00
Port A register
PORTA
R
Undefined
Port A MOS pull-up control register*² PAPCR
R/W H'00
Port A open-drain control register*² PAODR
R/W H'00
Notes: 1. Lower 16 bits of the address.
2. PAPCR and PAODR settings are prohibited in the ROMless version.
Address*¹
H'FEB9
H'FF69
H'FF59
H'FF70
H'FF77
Port A Data Direction Register (PADDR)
Bit
:
7
6
5
4
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR
cannot be read; if it is, an undefined value will be read.
PADDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their
output state or become high-impedance when a transition is made to software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
• Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin
an input port.
• Mode 6
Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing the bit to 0 makes the
pin an input port.
• Modes 4 and 5
The corresponding port A pins are address outputs irrespective of the value of bits PA4DDR to PA0DDR.
Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address output, while clearing
the bit to 0 makes the pin an input port.
Rev.6.00 Oct.28.2004 page 302 of 1016
REJ09B0138-0600H