HD64F2357F20V Datasheet, PDF (9/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Main Revisions for This Edition
Item
1.1 Overview
Table 1-1 Overview
4.1.3 Exception Vector Table
6.6.1 When DDS = 1
Figure 6-28 DACK Output Timing
when DDS = 1 (Example of DRAM
Access)
Page
5
72
149
Revision (See Manual for Details)
Product lineup
HD64F2398F20T*³ and HD64F2398TE20T*³ added
5V version
F-ZTAT
Version*
HD64F2357F20
HD64F2357TE20
HD64F2398F20
HD64F2398TE20
HD64F2398F20T *³
HD64F2398TE20T* ³
Note 3 added as follows
Note: 3. For the HD64F2398F20T and HD64F2398TE20T only, the
maximum number of times the flash memory can be reprogrammed is
1,000.
Description amended
In modes 6 and 7 the on-chip ROM ...In this case, clearing the EAE
bit in BCRL enables the 128-kbyte (256-kbytes)* area comprising
address H’000000 to H’01FFFF (H’03FFFF)* to be used.
Figure 6-28 amended
Write
HWR, (WE)
D₁₅ to D₀
6.6.2 When DDS = 0
150
Figure 6-29 DACK Output Timing
when DDS = 0 (Example of DRAM
Access)
Figure 6-29 amended
Write
HWR, (WE)
D₁₅ to D₀
6.8.2 Usage Notes
156
Figure 6-35(a) Example of Idle Cycle
Operation in RAS Down Mode (ICIS1
= 1)
Figure 6-35(b) Example of Idle Cycle
Operation in RAS Down Mode (ICIS0
= 1)
Figure 6-35(a) amended
External read
DRAM
T_I
T₁
T₂
T₃ T_cI
Figure 6-35(b) amended
External read
DRAM
T_I
T₁
T₂
T₃ T_cI
Rev.6.00 Oct.28.2004 page iii of xxiv
REJ09B0138-0600H