HD64F2357F20V Datasheet, PDF (488/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT
overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by
overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes
on Register Access.
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during
watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
0
1
Description
[Clearing condition]
(Initial value)
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the H8S/2357 Group if TCNT
overflows during watchdog timer operation.
Bit 6
RSTE
Description
0
Reset signal is not generated if TCNT overflows*
(Initial value)
1
Reset signal is generated if TCNT overflows
Note: * The modules within the H8S/2357 Group are not reset, but TCNT and TCSR within the WDT are reset.
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer
operation.
For details of the types of resets, see section 4, Exception Handling.
Bit 5
RSTS
Description
0
Power-on reset
(Initial value)
1
Manual reset*
Note: * Manual reset is supported only in the H8S/2357 ZTAT. In the models except the H8S/2357 ZTAT, only 0 should be
written to this bit.
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.
Rev.6.00 Oct.28.2004 page 458 of 1016
REJ09B0138-0600H