HD64F2357F20V Datasheet, PDF (123/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

(3) Default Priority Determination
When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated.
If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the
highest priority according to the preset default priorities is selected and has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5-8 shows operations and control signal functions in each interrupt control mode.
Table 5-8 Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt
Control ^Setting
Mode INTM1 INTM0
Interrupt
Acceptance Control
I
0
0
0
IM
2
1
0
× —*¹
Legend
: Interrupt operation control performed
×: No operation. (All interrupts enabled)
IM: Used as interrupt mask bit
PR: Sets priority
—: Not used
Notes: 1. Set to 1 when interrupt is accepted.
2. Keep the initial setting.
Default
8-Level Control _Priority
T
I2 to I0 IPR Determination (Trace)
× — —*²
—
IM PR
T
5.4.2 Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the
CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.
Figure 5-5 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the
interrupt controller.
[2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an
NMI interrupt is accepted, and other interrupt requests are held pending.
[3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is
accepted, and other interrupt requests are held pending.
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has
been completed.
[5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the
address of the first instruction to be executed after returning from the interrupt handling routine.
[6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the
address indicated by the contents of that vector address.
Rev.6.00 Oct.28.2004 page 93 of 1016
REJ09B0138-0600H