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HD64F2357F20V Datasheet, PDF (779/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series
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(5) Timing of On-Chip Supporting Modules
Table 22-30 lists the timing of on-chip supporting modules.
Table 22-30 Timing of On-Chip Supporting Modules
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Item
Condition A Condition B Condition C
Test
Symbol Min Max Min Max Min Max Unit Conditions
PORT Output data delay time t PWD — 100 — 50 — 75 ns Figure 22-86
Input data setup time t PRS
50 — 30 — 50 —
Input data hold time t PRH 50 — 30 — 50 —
PPG Pulse output delay time t POD — 100 — 50 — 75 ns Figure 22-87
TPU Timer output delay time t TOCD — 100 — 50 — 75 ns Figure 22-88
Timer input setup time t TICS 50 — 30 — 50 —
Timer clock input setup t TCKS
time
50 —
30 —
50 — ns Figure 22-89
Timer clock Single
pulse width edge
t TCKWH 1.5 —
1.5 —
1.5 — t cyc
Both
edges
t TCKWL 2.5 —
2.5 —
2.5 —
TMR
Timer output delay time tTMOD
Timer reset input setup tTMRS
time
— 100 — 50
50 — 30 —
— 75 ns Figure 22-90
50 — ns Figure 22-92
Timer clock input setup tTMCS
time
50 —
30 —
50 — ns Figure 22-91
Timer clock Single
pulse width edge
tTMCWH 1.5 —
1.5 —
1.5 — tcyc
Both
edges
tTMCWL 2.5 —
2.5 —
2.5 —
WDT Overflow output delay t WOVD — 100 — 50 — 75 ns Figure 22-93
time
SCI Input clock Asynchro- t Scyc
4
—4
—4
— t cyc Figure 22-94
cycle
nous
Synchro-
nous
6 —6 —6 —
Input clock pulse width
Input clock rise time
Input clock fall time
t SCKW
t SCKr
t SCKf
0.4 0.6 0.4 0.6 0.4 0.6 t Scyc
— 1.5 — 1.5 — 1.5 t cyc
— 1.5 — 1.5 — 1.5
Rev.6.00 Oct.28.2004 page 749 of 1016
REJ09B0138-0600H
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