HD64F2357F20V Datasheet, PDF (348/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

9.11.2 Register Configuration (On-Chip ROM Version Only)
Table 9-19 shows the port D register configuration.
Table 9-19 Port D Registers
Name
Port D data direction register
Port D data register
Port D register
Port D MOS pull-up control register
Note: * Lower 16 bits of the address.
Abbreviation R/W
PDDDR
W
PDDR
R/W
PORTD
R
PDPCR
R/W
Initial Value
H'00
H'00
Undefined
H'00
Address *
H'FEBC
H'FF6C
H'FF5C
H'FF73
Port D Data Direction Register (PDDDR) (On-Chip ROM Version Only)
Bit
:
7
6
5
4
3
2
1
0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR
cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
• Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin
an input port.
• Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O.
Port D Data Register (PDDR) (On-Chip ROM Version Only)
Bit
:
Initial value :
R/W
:
7
PD7DR
0
R/W
6
PD6DR
0
R/W
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD₇ to PD₀).
PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 318 of 1016
REJ09B0138-0600H