HD64F2357F20V Datasheet, PDF (462/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The
NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap
margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the
TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare
match B occurs.
Figure 11-11 shows the timing of this operation.
Compare match A
Compare match B
NDR
PODR
Write to NDR
Write to NDR
0 output 0/1 output
Write to NDR
Do not write ^here
to NDR here
0 output 0/1 output
Write to NDR
Do not write ^here
to NDR here
Figure 11-11 Non-Overlapping Operation and NDR Write Timing
Rev.6.00 Oct.28.2004 page 432 of 1016
REJ09B0138-0600H